The invention relates to the field of electronic packaging and interconnections.
A high-speed electronic module usually consists of interconnected individually packaged components mounted on a PCB board. For very high-speed data or microwave applications, ceramic substrates are usually used for packaging each individual component. Very high-speed communication modules can have a combination of very high-speed interconnects and numerous lower-speed I/O interconnects The combination of high speed connections and a large number of low speed connections make the integrated module design challenging. High speed interconnects between packages or modules require broadband connectors such as Anritsu xe2x80x9cVxe2x80x9d connectors or HP 2.4 mm, etc. These connectors have strict mechanical registration requirements for the center pin. In other words, the center pin needs to be very accurately aligned in 3 dimensions to transmission lines on the substrate. In addition, these connectors are large, usually much taller than any of the board and substrate dimensions. The low speed interconnections are interconnected through the use of area array techniques such as BGA, LGA, PGA, etc. However, most area array technologies use solder to provide the mechanical and electrical interconnection to the system. Soldered interconnects make it difficult to meet registration requirements of the broadband connector, due to form factor constraints and process engineering challenges, i.e. temperature control, module movement during process, and uneven package weight distribution required during reflow of the solder joints. In addition, CTE mismatch between substrate and PCB material is also of considerable concern, adding yet another constraint to area arrays requiring solder joints.
Traditional microwave packages are routed on the substrate surface. This approach is viable for low I/O counts but is not easily extendable to high pin count devices due to routing limitations.
The invention comprises a high-speed package design of integrated components, substrates, and a suspended printed circuit board (PCB). This high-speed package integrates high-speed signals with lower speed I/O""s, enabling a new generation of high pin count applications while maintaining the signal integrity of the high speed signals. This invention is valid for all substrate materials including plastic and ceramic. It comprises a protective package housing, preferably metal, having a housing lip, and an attached center pin, such as from a connector, which is also attached to the housing and abutting along the housing lip. For an accurate substrate alignment to the center pin, the substrate is mated to the housing lip, which serves as a ceiling and an alignment reference edge to the top surface of the substrate.
Alternatively, if signal registration to a second substrate within the same high-speed package is desired, the housing lip ensures that the top surface of both the first and the second substrate are coplanar and aligned with each other. An accurate, coplanar registration of high speed signal paths is guaranteed, facilitating interconnection between substrates by means such as by wire bonding. Moreover, an accurate alignment of the substrates minimizes the dimensions required of the wire bond for signal registration from one substrate to the other. The high-speed package design of this invention thus meet the strict mechanical requirements for accurate registration and signal integrity from a center pin to the underlying substrate, or alternatively, from the 2nd level high-speed interconnects on one substrate to another, for the very high speed I/O""s
In yet another embodiment, the housing lip serves as a housing base rather than the ceiling of the above described embodiment for the substrate and other underlying layers in the packaging. The principles of the invention remains the same, wherein the housing lip again serves as the alignment reference for the substrate, and thus once the first substrate abuts this alignment reference, the first substrate is in exact registration with a center pin, or easily wire bonded to other signal traces of an another substrate also aligned to the housing lip. In this embodiment, preferably a thin-film substrate with accurate thickness control is used for registration of the center pin to the first substrate. Since thin-film is typically thinner than multilayer substrates, the metal housing is preferably constructed so that the housing has a first height under the thin-film and a second height under the second substrate with the effect of aligning the top surfaces of both substrates, thus minimizing the dimensions of the ribbon-bond.
It is contemplated that variable number of substrates may be assembled with the high-speed package design of this invention. The numerous lower-speed 2nd level interconnects routed to the PCB are achieved in the format of various area array technologies. Specifically, an LGA (Land Grid Array) can be used to route numerous lower-speed I/O""s up to several gigabits per second. LGA socket provides the 2nd level interconnects between the individual component or the substrate and the PCB board. The LGA socket comprises of an interposer and spring-like contacts, which are assembled to the rest of the package through mechanical clamping. In the preferred embodiment, a back plate layer and screws are used to mechanically clamp together all intervening layers between the back plate and the substrate housing, thus eliminating the need for soldering and the attendant engineering challenges. The PCB may either xe2x80x9csuspendxe2x80x9d beneath the substrate sub-assembly in the xe2x80x9cfloatedxe2x80x9d substrate embodiment, or stacked over the substrate sub-assembly, as in the xe2x80x9cbottom-upxe2x80x9d version. The PCB, relative to the module back plate, is suspended by anchors that screw from the housing to the board. The substrate subassembly can be attached to the PCB via ways of mechanical clamping, epoxying or soldering. Such a package design partitions the regions of very high speed 2nd level interconnects and lower speed 2nd level interconnects so that all the high speed interconnects that require stringent mechanical tolerances reside within the substrate subassembly and the lower speed 2nd level interconnects that do not require stringent mechanical tolerances form the interface between the subassembly and the PCB. It thus accommodates the very different requirements of high speed and lower speed interconnects and ensures the integrity and manufacturability of the final module. It is understood that the various packaging layers described herein are merely illustrative, and varying layers or number of layers underlying the substrate is possible and not intended to limit the ability of this high-speed package design to provide accurate signal to substrate, or substrate-to-substrate registration.